PURPOSE: To prevent malfunction due to a transmission delay or a waveform distortion by devising the circuit such that a data latch circuit latches a parallel video data in N(≥16) bits and an N:M data selector circuit outputs an N bit parallel video data separately in each of M(≤N/2) bits.

CONSTITUTION: A 16-bit parallel video data signal PD is latched in an up-edge timing of a latch signal LS to give a latch output PD1, which is given to a 2:1 data select circuit 3, in which high-order 8-bit and low-order 8-bit are selected alternately as a select output PD2 by using a select signal DS. The output PD2 is converted into an ECL level via a TTL/ECL translator 4 and a resulting translator output PD3 is outputted to a shift register 5. Then the output PD3 is read by the shift register 5 by using a load clock signal fp and converted into a serial signal by using a shift clock signal fb and a serial video data signal SD is obtained. Thus, the malfunction due to a transmission delay or a waveform distortion is prevented.