PURPOSE: To reduce the number of gates by using a gate circuit inputting plural data strings in parallel and outputting them at the timing of a timing pulse, and a shift register inputting the output and outputting data in a prescribed order by a clock pulse.

CONSTITUTION: Plural data strings are inputted to the gate circuit 300 in parallel, and they are respectively outputted at the timing decided by the timing pulse. The outputs of the gate circuit 300 are inputted to the shift register 320 and data of the data strings are outputted in parallel by the clock pulse in the prescribed order. Thus, a counter and a box using a large number of gates can reduce the number of gates since they do not require many flip-flops.