PURPOSE: To constitute a shift register of one two-input data selecting circuit and one storage circuit by delaying a supplied reference clock to generate a different shift clock.

CONSTITUTION: A parallel-serial data converting part 1 consisting of shift registers 3 to 6 is provided where one bit of parallel data D2 from the external is inputted and stored in response to a shift clock L and serial data D1 from the preceding stage is inputted and stored in response to a different shift clock . Further, a shift clock control part 2 is provided which generates the shift clock L and the different shift clock in response to fundamental clocks 1 and 2 from the external and a data taking-in timing signal LD. Thus, shift registers 3 to 6 of the parallel-serial converting part 1 consist of only one two- input data selecting circuit and one storage circuit, and the number of transistors of a multibit parallel-serial converter is reduced.