PURPOSE: To relax conditions of the high-speed operation and to output a serial signal having a high repeat frequency by providing serial registers to which the same serial signal, the same load signal, and odd and even parallel signal are inputted and syntherizing outputs of them.

CONSTITUTION: The same shift signal SM and the same load signal SL are inputted to shift registers 2 and 3, and even signals P2∼P8 of parallel signals A and B are inputted to the register 2, and odd signals P1∼P7 of signals A and B are inputted to the register 3. Outputs taken into registers 2 and 3 in order are applied to one inputs of AND gates 5 and 6 of a selecting ciruit 8, and the signal SM is applied to the other input of the gate 5, and the signal to which the signal SM is inverted by an inverter 4 is applied to the other input of the gate 6. Outputs of gates 5 and 6 are synthesized by an OR gate 7 to output a serial signal SSE, thus relaxing conditions of the high-speed operation to output the serial signal SSE having a high repeat frequency.