PURPOSE: To improve the power consumption efficiency by shifting sequentially a shift register when a parallel signal of plural bits is set to the shift register and outputting selectively sequentially series signals outputted from the shift register.

CONSTITUTION: Signals D1∼D8 are set simultaneously to the shift register 1 by a set pulse S, signals D9∼D16 are set to a shift register 2 similarly and signals D17∼D24 are set to a shift register 3. The signals D1∼D24 in 24-bit are set to the shift registers 1∼3 while being split as parallel data in this way. A pulse P of a period T is generated from a pulse generating section 5, the pulse P is fed to the shift register 1 via a contact of a switch section 6 and fed to an octal counter 7. Since the shift register 1 is shifted sequentially by the pulse P, the signals D1∼Dn are extracted serially from the output terminal A and fed to an input terminal (a) of a matrix circuit 4. Thus, the signals D1∼D8 are outputted serially from the output terminal Z of the matrix circuit 4 and fed to a display section 8.