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Title:
PARALLELIZATION POSSIBILITY ANALYSIS SYSTEM OF PROGRAM
Document Type and Number:
Japanese Patent JPH05250175
Kind Code:
A
Abstract:

PURPOSE: To analyze the parallelization possibility of a program on a computer having a single CPU.

CONSTITUTION: A program input part 1 reads a program including a parallelization instruction line. A first program execution part 2 executes the program read by the program input part 1 in accordance with the processing sequence. A parallelization instruction line detection part 3 searches the parallelization instruction line in the program and detects a processing part for which a parallelization possibility analysis is to be performed. A processing sequence shuffling part 4 changes the execution sequence of the processing part detected by the parallelization instruction line detection part 3. A second program execution part 5 executes the program for which the processing sequence is changed. An acceptance or rejection decision part 6 compares the execution result of the program executed by the first program execution part 2 with the execution result of the program executed by the second program execution part 5. Thus, the parallelization possibility analysis can be performed without using a parallel computer.


Inventors:
TAKEUCHI YUKO
NONOMURA HITOSHI
Application Number:
JP4905492A
Publication Date:
September 28, 1993
Filing Date:
March 06, 1992
Export Citation:
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Assignee:
NEC CORP
NEC SOFTWARE LTD
International Classes:
G06F9/45; (IPC1-7): G06F9/45
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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