PURPOSE: To add simple hardware irrespective of the value of bit length, enabling generation of parity and improve performance by detecting faults of a series parallel converting element.
CONSTITUTION: Series data that make n bit length near the lead 101 of a parity allowing system a frame unit is stored successively in a shift register 1 by a clock 103. FF is cleared by clock 102 of the head of each frame, and the value of exclusive logical sum output prepared by a gate 2 by output 105 and series data is accumulated in clock 103 by FF3. When data for one frame are stored in the register 1, even number parity for data D1∼Dn of relevant frame is generated in FF3. Then, parallel data 106-1∼106-n and parity 105 are set in a register 5 by a frame clock 104. Thus, generation of parity is made possible by simple constitution, and capacity of the system is improved.
| JP3577289 | Optical signal processing method and optical signal processing device |
| JPH11177406 | INTEGRATED CIRCUIT |
| JPH0738551 | FRAME SYNCHRONIZING SYSTEM |
NISHIMURA KAZUO
TOKUSHIMA TAKASHI
NIPPON TELEGRAPH & TELEPHONE
| JPS57188157A | 1982-11-19 |