PURPOSE: To realize a parity generation circuit at serial data transfer with a simple circuit by using a binary counter so as to count a one level of a serial data to an input circuit thereby forming a parity bit of the serial data.
CONSTITUTION: A binary counter circuit 60 generating a parity bit from a serial transmission/reception data and a parity level selection circuit 80 selecting the level of the parity bit generated by the circuit 60 in an even number parity or an odd number parity are provided. Since the output of a data latch circuit 68 is inverted at each input of '1' level as a serial data STD, the output of the circuit 60 is an even number parity corresponding to the serial data STD. The output from the circuit 60 is outputted at the original level via a transfer gas 83 at the selection of the even number parity by the parity level selection circuit 80 and outputted via a transfer gate 82 after being inverted by an invert er 81 at the selection of odd number parity and outputted via a transfer gate 85 in the timing of a control signal T.
HIRAHARA JIRO
ABE AKITO
| JP46034455A | ||||
| JPS4948255A |