Title:
PATH TIMING DETECTION CIRCUIT AND ITS DETECTION METHOD
Document Type and Number:
Japanese Patent JP3358603
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a path timing detection circuit that can avoid its correlation arithmetic operation (accumulation) when a correlation length reaches a required length or over.
SOLUTION: When a power comparator 17 discriminates that a sum of an accumulator 13 accumulating results of correlation arithmetic operations between received data and a spread code exceeds a set threshold value 21, the power comparator 17 stops the accumulation by the accumulator 13. Thus, useless accumulation can be avoided.
Inventors:
Michihiro Ohsuge
Application Number:
JP31316699A
Publication Date:
December 24, 2002
Filing Date:
November 04, 1999
Export Citation:
Assignee:
NEC
International Classes:
H04B1/707; H04B1/709; (IPC1-7): H04B1/707
Domestic Patent References:
| JP11205283A | ||||
| JP832548A | ||||
| JP7235913A | ||||
| JP10200505A | ||||
| JP10308689A |
Attorney, Agent or Firm:
▲柳▼川 信
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