Title:
PATH TRANSISTOR LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JP3813307
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a path transistor logic circuit with small power consumption, small parasitic capacitance and capable of a high speed operation whose chip size is made small.
SOLUTION: The path transistor logic circuit is provided with a switch circuit 1 configured only with NMOS transistors(TRs) and with a voltage conversion circuit 2 that converts an output voltage of the switch circuit 1 into a full swing voltage. The voltage conversion circuit 2 is provided with a cross latch load circuit 3 consisting of PMOS TRs P1, P2 and a drive circuit 4 consisting of NMOS TRs N1, N2. An output voltage of the switch circuit 1 is fed to gate terminals of the NMOS TRs N1, N2, and a gate voltage of the PMOS TRs P1, P2 is controlled by the drain voltage. Since the gate terminal of the NMOS TRs N1, N2 keeps a high resistance, no DC current is supplied to the switch circuit 1 and an output voltage of the current conversion circuit 4 is not affected by an ON-resistance of the switch circuit 1.
Inventors:
Shuji Koike
Application Number:
JP17066797A
Publication Date:
August 23, 2006
Filing Date:
June 26, 1997
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H03K19/0185; H03K19/0944; H03K19/096; (IPC1-7): H03K19/0185; H03K19/0944; H03K19/096
Domestic Patent References:
| JP10341147A | ||||
| JP8321770A |
Attorney, Agent or Firm:
Kazuo Sato
Masamitsu Sato
Hidetoshi Tachibana
Yasukazu Sato
Masamitsu Sato
Hidetoshi Tachibana
Yasukazu Sato