Title:
PATTERN FORMING METHOD
Document Type and Number:
Japanese Patent JPS61121332
Kind Code:
A
Abstract:
PURPOSE:To improve productivity reducing the process by suitable combination of an upper layer resist member, a lower layer resist member, developer and liquid rinse as the case may be. CONSTITUTION:A lower resist thick layer made by a resist member not contained an Si, which can be etched by means of plasma treatment and is insoluble to developer using for formation of an upper layer pattern, and an upper resist thin film made by a resist member contained an Si for sensitive ionizing radiation possessed anti-plasma etching are formed by turns on the surface of a member to be produced. For example, which is provided by resoluting polyvinylphenol to cychohexane is spin-coated on an Si substrate 1 and is baked, then a lower layer resist film 2 is provided. The resolution, which is provided by dissolving silylated polymethylsilsesquioxane in toluene, is spin-coated on the lower layer resist film 2 and is baked, then a upper layer resist film 3 is obtained. Subsequently, a latent image is formed to the upper layer resist thin film by projecting an image pattern of ionizing radiation, and latent image is developed, then plasma treatment is performed by means that the upper layer resist pattern is designated as a mask, then the upper layer resist pattern is duplexed to the lower layer resist thin film.
Inventors:
MIYAGAWA MASASHI
YONEDA YASUHIRO
FUKUYAMA SHUNICHI
NISHII KOTA
YONEDA YASUHIRO
FUKUYAMA SHUNICHI
NISHII KOTA
Application Number:
JP24236484A
Publication Date:
June 09, 1986
Filing Date:
November 19, 1984
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G03F7/26; G03F7/20; H01L21/027; H01L21/30; (IPC1-7): G03F7/20
Attorney, Agent or Firm:
Aoki Akira
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