Title:
PATTERN GENERATOR
Document Type and Number:
Japanese Patent JPH0338784
Kind Code:
A
Abstract:
PURPOSE: To eliminate time and labor to assemble a ROM in which a bit pattern is written with address correspondence and an address control counter separately by unifying them in one single package.
CONSTITUTION: The ROM 10 in which the bit pattern is written with the address correspondence and the address control counter 9 which outputs sequential pattern data by designating the address of the ROM at every input of an external clock from a pin 12 are unified in the package 9. Thereby, it is possible to easily output an arbitrary sequential pattern only by inputting a clock and a reset signal from the outside, and also, to make an output pattern into large capacity as simplifying and facilitating cascade connection when it is used.
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Inventors:
MORITA TOSHIYA
Application Number:
JP17350389A
Publication Date:
February 19, 1991
Filing Date:
July 05, 1989
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06T11/20; (IPC1-7): G06F15/72
Attorney, Agent or Firm:
Hiroaki Tazawa (2 outside)
Next Patent: JPH0338785