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Patent Searching and Data


Title:
PCM-SYSTEM SIGNAL RECORDER/REPRODUCER
Document Type and Number:
Japanese Patent JPS5587311
Kind Code:
A
Abstract:

PURPOSE: To prevent the evil effect of the dropout to the generation of the reading clock by producing the reading clock through the fixed free-running circuit.

CONSTITUTION: Vertical synchronous signal Sb isolated from the reproduced PCM video signal receives the delay of a fixed time via V delay circuit F, and then signal Sc equivalent to start signal Sd isolated through delay circuit A is generated. Thus even if signal Sd lacks due to the dropout or the like, signal Sc resets H counter G via OR circuit E. As a result, counter G has the free running via oscillator C to generate the reading clock with no evil effect given by the dropout, thus securing the assured reading for the fixed number of the data groups. The free-running counter G is stopped via V counter H and others after counting the fixed number of the data groups.


Inventors:
SUDOU KENGO
SASADA TAIZOU
Application Number:
JP16545278A
Publication Date:
July 02, 1980
Filing Date:
December 23, 1978
Export Citation:
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Assignee:
SHARP KK
International Classes:
H03M7/00; G11B5/09; G11B20/10; H04B14/04; (IPC1-7): G11B5/09; H04B12/02