Title:
PDM ACCUMULATOR SECONDARY LOOP FILTER CONVERTING MULTI-BIT PHASE ERROR INPUT TO FORWARD/DELAY CONTROL FOR STEPWISE CLOCK GENERATOR
Document Type and Number:
Japanese Patent JP3163123
Kind Code:
B2
Abstract:
PURPOSE: To convert a multi-bit phase error input signal, with respect to a phase locked loop, into a high resolution control signal for a polyphase clock generator that supplies a sample clock output signal with a sample clock cycle period.
CONSTITUTION: In a pulse density modulation(PDM) accumulator secondary loop filter, a phase error signal is given to a proportional accumulator 102, in which a phase error term proportional to a phase error input signal is obtained and it is fed to both an integration device accumulator 108 and an integration + proportion adder circuit 110. Then an integration + proportional output term is fed to a PDM accumulator 120. The PDM accumulator 120 interfaces the integration + proportion term to a polyphase clock generator. An adder 122 stores the integration + proportion term. Every time an overflow or underflow takes place in the adder 122, the polyphase clock generator jumps one phase period via a shift/idle signal PJEN.
Inventors:
He Won
Howard Wilson
Jesus Guinea
Howard Wilson
Jesus Guinea
Application Number:
JP19467591A
Publication Date:
May 08, 2001
Filing Date:
May 02, 1991
Export Citation:
Assignee:
National Semiconductor Corporation
International Classes:
H03L7/06; H03L7/093; H04L7/033; (IPC1-7): H03L7/093
Other References:
【文献】英国特許出願公開2201869(GB,A)
Attorney, Agent or Firm:
Kazuo Kobashi (1 person outside)