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Title:
PEAK CLIPPING CIRCUIT
Document Type and Number:
Japanese Patent JPS58108814
Kind Code:
A
Abstract:

PURPOSE: To process a high frequency signal adequately, by improving output nonlinearity and giving a buffer effect to a peak clipping circuit suitable for a white signal clipping circuit, etc., used for the processing of a white signal of a video signal of a television receiver and a video tape recorder.

CONSTITUTION: The common load resistance 64 of differential amplifiers 30 and 32 is connected to the transistors (TR) 36 and 40 of both differential amplifiers 30 and 32, and a peak clip output appearing at the resistance 64 is led out from an output terminal 68 through a buffer circuit 66 and all fed back as inverted phase inputs to the differential amplifiers 30 and 32 through a feedback circuit 70. For this purpose, the differential amplifier 30 functions as a buffer circuit having a gain 1 and resistances 54 and 56 connected to the emitter for preventing oscillation are set to adequate values to decrease its gain. The diffeential amplifier 32 functions as a comparator by setting its closed loop gain large. Thus, a clip level is set easily and nonlinearity of a base-emitter voltage is improved.


Inventors:
IZAWA KAORU
ISHIDA MASAHARU
Application Number:
JP20889681A
Publication Date:
June 29, 1983
Filing Date:
December 23, 1981
Export Citation:
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Assignee:
ROHM KK
International Classes:
H03G11/00; (IPC1-7): H03G11/00
Attorney, Agent or Firm:
Shoichi Unemoto



 
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