To provide a peak detection circuit capable of suppressing a reduction of an output signal.

A resistor 6 is connected between a source terminal of a MOSFET 4 of a p-channel parallel-connected to a MOSFET 2 of an n-channel and a terminal 10 to which a power supply voltage VDD is applied, and a resistor 7 is connected between the source terminal of a MOSFET 5 of the p-channel parallel-connected to a MOSFET 3 of the n-channel and the terminal 10 to which the power supply voltage VDD is applied. An input signal INP is inputted into respective gate terminals of the MOSFETs 2, 5, and an inversion signal INN of the input signal INP is inputted into the respective gate terminals of the MOSFETs 3, 4.

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