PURPOSE: To achieve high speed response without generating such a situation that a peak value is not held, by constituting the title circuit so that the static comparator of a peak holding circuit always has positive offset voltage.

CONSTITUTION: In a peak holding circuit, a holding capacity 9 receiving an input signal through an analogue multiplexer 7, a static comparator 6 and the output circuit connected to the capacity 9 are provided and this circuit is constituted so that the comparator 6 always has positive offset voltage. For example, when the P channel MOS transistor connected to the power supply voltage of the first branch in the differential amplifying stage therein is set to M1, the channel width and length of the transistor are set to W1 and L1, the P channel MOS transistor connected to the power supply voltage of the second branch is set to M2 and the channel width and length of the transistor are set to W2 and L2, the circuit is formed so as to satisfy W1/L1<W2/L2. As a result, it is eliminated that holding voltage becomes higher than input voltage and the lowering factor of yield can be removed.