Title:
PEELING METHOD OF RESIST AND ITS DEVICE
Document Type and Number:
Japanese Patent JPH10321603
Kind Code:
A
Abstract:
To restrain generation of popping during peeling of resist on a semiconductor wafer after ion implantation and peel resist at a high rate.
A set layer 27 is peeled at a low temperature of at 100°C or thereabout, by raising a semiconductor wafer 25 from a stage 16 with a heating means 19 by an auxiliary stage 21, and the auxiliary stage 21 is lowered after the set layer 27 is peeled to be brought into contact with the stage 16 heated by the heater 19 for peeling a normal layer 26 at the state of a high temperature of 200 to 300°C.
Inventors:
MOTOMURA HIDEOMI
Application Number:
JP12965897A
Publication Date:
December 04, 1998
Filing Date:
May 20, 1997
Export Citation:
Assignee:
SONY CORP
International Classes:
H01L21/302; H01L21/027; H01L21/3065; H01L21/68; H01L21/683; (IPC1-7): H01L21/3065; H01L21/027; H01L21/68
Attorney, Agent or Firm:
Osamu Matsumura