PERIPHERAL DEVICE USED FOR COMPUTER SYSTEM, AND ITS CONTROL METHOD

Japanese Patent JP3188840

B2

PROBLEM TO BE SOLVED: To reduce the power consumption by properly stopping respective circuits in the peripheral device according to the state transition of data transfer operation while data are transferred between a computer system and the peripheral device.
SOLUTION: This device is equipped with an MPU 10 which controls the operations of respective parts, a 1st sequencer circuit 21 which can control data interchange through a host interface circuit 31 instead of the MPU 10, and a 2nd sequencer circuit 22 which can control data interchange through a memory interface circuit 32 instead of the MPU 10. The MPU 10 of high power consumption is actuated only at necessary irreducible time, for example, when a command from a computer system side is processed, and stopped by transferring the control to the sequencer circuits 21 and 22 in other periods. The 1st sequencer circuit 21 or 2nd sequencer circuit 22 is also actuated only at necessary irreducible time and stopped by transferring the control to the other sequencer circuit 22 or 21 in other periods.

JP2007141020	DATA PROCESSOR AND ELECTRONIC EQUIPMENT
JP6376567	Processor with operating frequency information to guarantee operation in high temperature events
WO/2019/013840	CLOCK FREQUENCY CONTROL SYSTEM

Takuji Matsushiba
Satoshi Karube

JP15365796A

July 16, 2001

June 14, 1996

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International Business Machines Corporation

G06F1/04; G06F1/16; G06F1/32; G06F1/26; G06F3/00; G06F13/12; G06K17/00; (IPC1-7): G06F13/12; G06F1/04; G06F1/32

JP6208534A
JP7295695A
JP6222862A
JP566756U

Jiro Yamamoto (2 outside)

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