Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
PHASE ADJUSTING CIRCUIT
Document Type and Number:
Japanese Patent JPS61255120
Kind Code:
A
Abstract:

PURPOSE: To obtain a circuit attaining phase adjustment in the unit of a reciprocal of an integer part of a bit length with simple circuit constitution by adopting the constitution that an input data signal is written by a clock pulse having N-time (N is an integer being ≤2) of a bit frequency of the input data signal.

CONSTITUTION: The frequency of a write clock pulse (c) is selected twice of that of a bit clock signal (b) of a data signal (a) fed to a data input 102. When a control input 104 of an EX-OR 3 is logical '0', the clock pulse (c) becomes the clock input of a shift register 1 as it is, a data output shown in figure (d) is obtained for an output 105 of an FF 1a and a data output shown in figure (d) is obtained at an output 106 of an FF 1d. When the control input 104 of the EX-OR 3 is logical '1', the clock input of the shift register 1 is inverted (figure f), and a data output shown in figure (g) is obtained at the output 105 of the FF 1a and a data output shown in figure (h) is obtained at the output of the FF 1d. Thus, the phase is adjusted in the unit of 1/4 bit within the range of 2-bit length.


Inventors:
ABE HIKARI
Application Number:
JP9714585A
Publication Date:
November 12, 1986
Filing Date:
May 08, 1985
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
H03K5/135; G06F1/04; H03M9/00; (IPC1-7): G06F1/04; H03K5/135; H03M9/00
Domestic Patent References:
JPS5161249A1976-05-27
JPS57210722A1982-12-24
Attorney, Agent or Firm:
Uchihara Shin