Title:
相変化メモリアレイのセットプログラミング方法及び書き込みドライバ回路
Document Type and Number:
Japanese Patent JP4767559
Kind Code:
B2
Abstract:
The method involves applying a set current pulse having predetermined stages to phase-change memory cells of the array to change the cells to the set resistance state. The minimum current level of the set current pulse applied to the memory cells in any stage is higher than the reference current level for the cells of the array. A given current level of the set current pulse is sequentially reduced from stage to stage. An independent claim is also included for a write drive circuit of phase-change memory.
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Inventors:
Chokichi
Kino
Guo Tadane
Zhao Kaji
Kino
Guo Tadane
Zhao Kaji
Application Number:
JP2005062852A
Publication Date:
September 07, 2011
Filing Date:
March 07, 2005
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C13/00; G11C13/02; G11C16/02; G11C16/10; G11C19/08; H01L27/10; H01L27/105; H01L27/115
Domestic Patent References:
| JP2003298013A | ||||
| JP2003100085A | ||||
| JP2005196954A |
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro