To provide a phase comparator and a clock generating circuit, which can compare a phase of a first clock signal with the one of a second clock signal accurately.

A double phase comparator 6 makes both of signals K and D to L level and delays the phase of a feedback clock signal FBCLK when the feedback clock signal FBCLK in the leading edge and the trailing edge of an internal clock signal is H level and L level respectively. The double phase comparator 6 makes both of signals K and U to L level and advances the phase of the feedback clock signal FBCLK when the feedback clock signal FBCLK in both edges is L level and H level respectively. If the level of the feedback clock signal FBCLK in both edges matches, the double phase comparator 6 makes signal K to H level and stops phase control of the feedback clock signal FBCLK.