PURPOSE: To improve the drawing response speed and jitter compression ability, by performing the phase comparison between input signal and reference phase signal and constituting the counter circuit counting the phase comparison signal with the first and the second memories and shift register.

CONSTITUTION: The input signal (a) and the reference phase signal (f) of the output of the frequency division circuit 5 are compared at the phase comparison circuit 1 and the phase comparison signal (b) is input to the count circuit 2. The circuit 2 counts the signal (b) and when the content of count reaches specified set value, the control signal (c) is fed to the clock control circuit 3. The circuit 3 adds the high speed clock (d) to the circuit 5 to perform insertion or deletion of one clock according to the signal (c). The circuit 2 has the second memory 32 to write in the output of the first memory 31 and the output signal (k) of the memory 32 and the signal (b) are taken as readout address for the readout of the memory 31 and the control signal (c) is output when specified value is obtained. Further, when the signal (b) is consecutively fed to the shift register for a given number, the signal (c) is output from the memory 31. Further, by the selection of the memory 31, the drawing and jitter compression characteristics can arbitrarily be set.