PURPOSE: To attain phase control independently of a pulse width of a comparison signal by providing a circuit keeping phase information relating to a reference signal and the comparison signal during the control period.

CONSTITUTION: A comparison signal NCK formed from a 1/N frequency divider 18 is inputted to a D-FF 15 as a clock and a reference signal (f) is inputted to a D-FF 15 as a data. An output Q of the D-FF 15 is the phase information between the reference signal (f) and the comparison signal NCK and inputted to a NAND gate 16. On the other hand, a differentiation circuit 14 differentiates the leading of the reference signal (f) to generate a differentiation pulse, which is inputted to the NAND gate 16 and the pulse is ANDed with the phase information from the D-FF 15, the result is inputted to an AND gate 17 as the phase control signal to apply phase control. Thus, the phase control is attained independently of the pulse width of the comparison signal NCK.