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Title:
PHASE DETECTOR
Document Type and Number:
Japanese Patent JPS5547734
Kind Code:
A
Abstract:

PURPOSE: To minimize the production of error voltage due to the effect of ghost and noise and to make earlier the drawing time, by taking logical product between the first phase cimparison pulse, second phase comparison pulse and condensation and rarefaction wave.

CONSTITUTION: The horizontal synchronizing signal separated at the synchronizing separation circuit 12 is fed to the NAND circuit 14 and AND circuir 15 at the phase detection circuit 13. To the NAND circuit 14 and the AND circuit 15, the output of frequency division of the output of the voltage controlled oscillator 20 with the frequency divider 21, and the condensation and rarefaction wave in which the leading and the vicinity of horizontal synchronizing signal produced by the output pulse of the frequency divider 21 added to the condensation and rarefaction wave generator 22 is taken as logical 1 and the time being 0 is increased far from the leading and the vicinity, are fed. The ouput of the middle point of the junction between the filed effect transistors 16 and 17 to which the output of the NAND circuit 14 and AND circuit 15 is fed, is fed to the low pass filter 23.


Inventors:
SATOU KENJI
Application Number:
JP12075978A
Publication Date:
April 04, 1980
Filing Date:
September 30, 1978
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H03K9/04; H03K5/26; H03L7/08; H03L7/085; H03L7/089; (IPC1-7): H03K5/26; H03K9/04; H03L7/08



 
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