Title:
PHASE INDETERMINACY ELIMINATOR
Document Type and Number:
Japanese Patent JP3300040
Kind Code:
B2
Abstract:
PURPOSE: To reduce an error in a transmission digital signal by detecting a frame pattern to be transmitted, and correcting the phase of a carrier outputted from a carrier generation circuit so as to detect a normal frame pattern.
CONSTITUTION: A carrier phase correction means 2 corrects the phase of the carrier supplied from the carrier generation circuit 4 to a phase rotating circuit 3 so as to set the frame pattern detected by a frame pattern detecting means 1 as the normal frame pattern. In other words, when the phase of the carrier sent out from the carrier generation circuit 4 shows θt+π/2, θt+π, and θt+3π/2, the phase is corrected to θt+0. When the carrier with phase of θt+0 is inputted to the phase rotating circuit 3, a normal digital signal can be reproduced, and the normal frame pattern can be detected by the frame pattern detecting means 1. Thereby, the configuration of a demodulator can be simplified, and the error in the transmission digital signal can be reduced.
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Inventors:
Takanori Iwamatsu
Application Number:
JP18218292A
Publication Date:
July 08, 2002
Filing Date:
July 09, 1992
Export Citation:
Assignee:
富士通株式会社
International Classes:
H04L7/08; H04L27/38; (IPC1-7): H04L27/38; H04L7/08
Domestic Patent References:
| JP43639A | ||||
| JP5451363A |
Attorney, Agent or Firm:
Hideo Takino (1 outside)
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