Title:
Phase interpolation machine
Document Type and Number:
Japanese Patent JP6059551
Kind Code:
B2
Abstract:
An exemplary phase interpolator includes a first to a fourth differential pair. Each of the differential pairs includes a first and a second transistor and a stabilizing capacitor connected between a source coupled node and a reference voltage. The phase interpolator also includes a plurality of current sources and a group of switches to switch connections between the source coupled nodes of the differential pairs and the current sources so that (i) a first operating current is supplied to a first selected one of the first and second differential pairs and (ii) a second operating current is supplied to a second selected one of the third and fourth differential pairs. Drains of the first transistors in the differential pairs are commonly connected and drains of the second transistors in the differential pairs are commonly connected to form a first and a second output node so that a differential output signal is output.
Inventors:
Nobuhiro Yanagisawa
Application Number:
JP2013028156A
Publication Date:
January 11, 2017
Filing Date:
February 15, 2013
Export Citation:
Assignee:
Mega Chips Co., Ltd.
International Classes:
H03H11/20
Domestic Patent References:
| JP2007149207A | ||||
| JP2003195956A | ||||
| JP2003037458A |
Foreign References:
| US20040052323 | ||||
| US20100026367 | ||||
| US7233173 | ||||
| US20090195286 | ||||
| US7750707 |
Attorney, Agent or Firm:
Yoshitake Hidetoshi
Takahiro Arita
Takahiro Arita