Title:
位相ロックループ回路
Document Type and Number:
Japanese Patent JP2006514485
Kind Code:
A
Abstract:
A PLL circuit comprising a loop filter with at least a first and a second bandwith is provided. The first bandwith of the loop filter is determined by a first network of circuit components and used out of the linear range of the PLL circuit and the second bandwith is determined by a second network of circuit components and used within the linear range of the PLL circuit. A node of said second network is charged to a voltage level given by a node of said first network while the second network is switched off. When the second network is switched in, no long lasting charging process is required. Therefore, the lock time of the PLL circuit is reduced.
Inventors:
Malton, Walter
Application Number:
JP2004569007A
Publication Date:
April 27, 2006
Filing Date:
March 07, 2003
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03L7/107; H03H1/02; H03L7/093; H03L7/18; H03L7/089
Attorney, Agent or Firm:
Tadahiko Ito