Title:
PHASE LOCKED LOOP CIRCUIT
Document Type and Number:
Japanese Patent JP2735092
Kind Code:
B2
Abstract:
PURPOSE: To obtain a highly stable self-running frequency by applying temperature compensation to the self-running frequency control for a PLL circuit.
CONSTITUTION: When an input signal 11 is interrupted, an output of an interrupt detection circuit 5 is inverted and a selector 6 selects an output of a variable delay circuit 7 whose delay is controlled by an output of a memory 8. An output of a phase comparator 1 is a pulse having a duty ratio proportional to the delay of the variable delay circuit 7, the pulse is smoothed by a filter 2 to be a control input voltage of a voltage controlled oscillator 3. A temperature detection circuit 9 detects a change in an ambient temperature and temperature compensation data corresponding to its output are outputted to the memory 8 and its output controls a delay in the variable delay circuit 7 to control a control input voltage of the voltage controlled oscillator 3. Thus, the temperature compensation for the self-running frequency is realized by storing the temperature compensation data to the memory 8 in advance.
Inventors:
KOBAYASHI TOSHIAKI
Application Number:
JP3051194A
Publication Date:
April 02, 1998
Filing Date:
February 28, 1994
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
H03L1/02; H03L7/14; (IPC1-7): H03L7/14; H03L1/02
Domestic Patent References:
| JP344214A | ||||
| JP661850A | ||||
| JP5648726A | ||||
| JP6448933U |
Attorney, Agent or Firm:
Yosuke Goto (2 outside)