To attain high speed phase synchronization locking, with respect to a phase locked loop(PLL) that synchronizes the phase of the output signal of a voltage controlled oscillator with the phase of an input signal.

A phase comparator 5 compares the phase of an input signal with the phase of a frequency dividing output signal which results from frequency-dividing the output of a voltage-controlled oscillator 1 with a frequency divider 6, and an output signal from the phase comparator is used for the control voltage of the voltage-controlled oscillator 1 in the phase-locked loop. The phase-locked loop circuit is provided with a lock control section 8 that controls 1st and 2nd changeover circuits 2, 3 in such a way that whether or not a frequency of an input signal is higher or lower than the center frequency is discriminated in the locking, a control voltage VCw with a lower limit frequency is selected when it is higher, or a control voltage VCh with a higher limit frequency is selected when it is lower, and the selected control voltage is given to the voltage-controlled oscillation 1 in place of the control voltage from the loop filter 4.