PURPOSE: To reduce the influence of a skew upon a PLL and to stabilize the formation of a phase locked loop clock by detecting the skew and changing the frequency dividing phase of a frequency divider to reduce a phase shift between a horizontal synchronizing signal(HS) and a clock (fH).

CONSTITUTION: A skew detector 16 is constituted of a means for detecting the leading edge of an HS and a comparator to detect the leading edge of the HS (HS detecting signal) and count up a period from one HS detecting signal up to the succeeding HS detecting signal. When a skew is included in a video input, the detector 16 detects the skew and outputs a skew detecting signal, so that the frequency divider 16 is reset and the phase of the clock fH is returned to the original state. Namely, the leading edge of the HS coincides with the timing for turning the counter value of the divider 16 to '0'. Since the operation of a phase comparator 12 is stopped in this case, the influence of the skew upon the PLL can be reduced and the formation of the PLL clock can be stabilized.