To correct a phase difference without depending on an inputted digital signal pattern by temporarily discriminating to a most reliable value based on a data line of a digital information signal from an A/D conversion means, outputting a difference between respective digital information signals from the A/D conversion means as a phase error component and adding them at every sampling timing.

In a loop consisting of a second operation circuit 20, a second switch circuit 21 and a delay element 22, since a signal of CTL1 is an H between that a temporary discrimination result of a temporary discrimination circuit 16 in an error component output means 2a is '+1' or '-1' the second switch circuit 21 is connected to a terminal H side, and the signal from the second operation circuit 20 is inputted. When the temporary discrimination result is '0', the signal of CTL2 becomes the H, and a third switch circuit 23 is connected to the terminal H side. Since the error component from the error component output means 2a is added to the signal, and the signal is outputted as the error signal, the error signal is outputted stably without depending on the signal pattern.