Title:
PHASE LOCKED LOOP, PHASE DETECTOR, AND METHOD FOR GIVING VARIABLE DELAY TO INPUT WAVEFORM
Document Type and Number:
Japanese Patent JPH05300140
Kind Code:
A
Abstract:
PURPOSE: To provide a novel phase detector for phase locked loop(PLL) for retrieving bit clocks. CONSTITUTION: A phase detector 1 uses a plurality of variable delay devices 20 and 21 and has a fixed gain area which is a percentage of a clock period over the expanded frequency range of a VCO(voltage controlled oscillator) so that one PLL chip can operate in several applications at widely different frequencies.
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Inventors:
MAAKU SHII GUREISHIYAATO
TOOMASU KOON
TOOMASU KOON
Application Number:
JP2901793A
Publication Date:
November 12, 1993
Filing Date:
February 18, 1993
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INC
International Classes:
H03L7/081; H03L7/085; H04L7/033; (IPC1-7): H04L7/033; H03L7/085
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)