Title:
PHASE LOCKED LOOP
Document Type and Number:
Japanese Patent JP2016021691
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To decrease power consumption of a phase locked loop by suppressing frequency drift of an output signal from a voltage controlled oscillator.SOLUTION: A DLL 10 includes a delay circuit 10A for delaying a fundamental clock signal Clk, a phase comparator 10B for comparing phases of the fundamental clock signal Clk and an output signal of the delay circuit 10A, and outputting a phase difference signal d2 according to the phase difference, and a loop filter 10C for converting the phase difference signal d2 to a control voltage V2. If operating time after operation start is longer than a predetermined setting time, a control circuit 9 turns off power to a variable divider 2, a reference oscillator 3, a reference divider 4, a phase comparator 5, and a charge pump 7, with a power supply control signal Sp, and turns off a switch 8 with a switch control signal Ss. Control of a voltage controlled oscillator 1 is switched from control with a control voltage V1 to control with the control voltage V2.SELECTED DRAWING: Figure 1
Inventors:
NAKAMURA MITSUO
SHIBATA SHINTARO
SHIBATA SHINTARO
Application Number:
JP2014144822A
Publication Date:
February 04, 2016
Filing Date:
July 15, 2014
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H03L7/087
Attorney, Agent or Firm:
Hidekazu Miyoshi
Rie Kudo
Rie Kudo