Title:
位相同期回路
Document Type and Number:
Japanese Patent JP4421467
Kind Code:
B2
Abstract:
The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.
Inventors:
Shiro Michimasa
Takashi Morie
Yoshifumi Okamoto
Kazuaki Sogawa
Yuji Yamada
Takashi Morie
Yoshifumi Okamoto
Kazuaki Sogawa
Yuji Yamada
Application Number:
JP2004374265A
Publication Date:
February 24, 2010
Filing Date:
December 24, 2004
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
H03L7/093; H03L7/08; H03L7/107
Domestic Patent References:
| JP2002359555A | ||||
| JP2003078410A | ||||
| JP10032480A |
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori