PURPOSE: To suppress the jitter component of a reference clock signal inputted to a phase synchronized oscillator circuit.

CONSTITUTION: A frequency divider circuit 1 time-averages a jitter coming by being superimposed on the reference clock signal (a) and a cycle measuring circuit 2 measures the cycle of the change of a carry signal (c) with a high speed clock signal (b). An arithmetic processing circuit 3 statistically processes a cycle data signal (d) and controls a frequency dividing rate data signal (e) deciding the frequency dividing rate of a frequency divider circuit 4. The frequency divider circuit 4 divides the high speed clock signal (b) with the frequency dividing rate corresponding to the frequency dividing rate data signal (e) and outputs the reference signal (f) of the phase synchronized oscillator circuit 5.