To generate two precisely phase-synchronized clocks while reducing the jitters by generating different-frequency clocks, which are a clock to be used by an internal circuit and a board system clock, by only one PLL.

A logic device 4 which generates clocks according to the output signal 20 of a voltage-controlled oscillator circuit 3 is composed of a circuit which mainly divides the frequency of a clock and has a function of outputting many clocks differing in frequency division rate. In this case, clock signals 13 and 14 of two systems are outputted. The different-frequency clocks which are the clock to be used by the internal circuit 15 and the board system clock 11 can be generated by only one PLL and the jitters of the clock signals are made less than those when two PLLs are used. Further, delay variation due to a dummy cell and long wiring is suppressed. Consequently, the AC specification margin of a semiconductor integrated circuit is greatly reducible.