PURPOSE: To stably change the phase of input signal, by taking either of the 1/2 frequency dividing circuit signals based on the input signal as the identifying clock with the polarity discrimination circuit, taking another as the identified input, and selecting and outputting the polarity of the output of the 1/2 frequency dividing circuit.

CONSTITUTION: The signal which is obtained by delaying 302 one of the signals branched from the binary input signal, and the input signal are fed to the detection circuit 303 consisting of the exclusive logical sum circuit, the output of the circuit 303 is fed to the variable pulse width pulse generation circuit 307, and the output is given to the 1/2 frequency dividing circuit 305 consisting of FF. Further, the polarity discrimination circuit 503 consisting of FF takes either one of the signals from the circuit 305 as the identifying clock and another as identified signal input, and the polarity of the output of the circuit 305 is selected and outputted with the polarity selection circuit 504 consisting of exclusive logical sum circuit. Thus, the phase of the input signal can stably be changed.