Title:
LEVEL DETECTING CIRCUIT AND A/D CONVERTER USING THE SAME
Document Type and Number:
Japanese Patent JP3138090
Kind Code:
B2
Abstract:
PURPOSE: To provide a level detecting circuit adapted to the use of an A/D converter by providing a timer, a sampling circuit, a counter, a decoder, and a holding circuit which holds the output of the decoder at the end of a determined period.
CONSTITUTION: This detecting circuit consists of a sampling circuit 11, a counter 15, a timer 16, D-FFs 18 to 21, etc. The output of the counter 15 held by the D-FF 21 is applied as data to a time constant control circuit 22, and the output of the D-FF 20 is applied as a clock to the time constant control circuit 22. Consequently, the output which controls the time constant of a variable integration circuit is generated from the time constant control circuit 22. That is, when an input signal in the high level or an input in the low level continues, the time constant of the variable integrating circuit is reduced to constitute an A/D conversion circuit having good following capacity; and when the level of the input signal is balanced, the time constant of the variable integration circuit is increased to constitute an A/D conversion circuit having high stability.
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Inventors:
Onnaya Masato
Application Number:
JP31674992A
Publication Date:
February 26, 2001
Filing Date:
November 26, 1992
Export Citation:
Assignee:
Sanyo Electric Co., Ltd.
International Classes:
H03M3/02; (IPC1-7): H03M3/02
Domestic Patent References:
| JP63142724A | ||||
| JP63286025A | ||||
| JP3158020A |
Attorney, Agent or Firm:
Masamasa Shibano