PURPOSE: To judge the bus cycle end of data stored in a storing buffer with a microprogram by providing this pipeline controller with an address output starting signal suppressing circuit for suppressing the output of an address output starting signal at the times of inputting a microinstruction(MI) for instructing the execution of operand fetch to be executed without starting a bus cycle.

CONSTITUTION: When the bus cycle of data stored in the storing buffer 102 is not ended at the time of generating an MI for instructing the execution of operand fetch to be executed without starting the bus cycle from a control part 109, the execution of the MI concerned is aborted. Although the MI is executed after ending the bus cycle, the output of an address output start signal 103 is inhibited by an address output start signal suppressing circuit 110. Thus, the bus cycle end of the data stored in the buffer 102 is judged by the microprogram.