Title:
MIS SEMICONDUCTOR DEVICE AND ITS MANUFACTURE
Document Type and Number:
Japanese Patent JP3230504
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve breakdown voltage a against overvoltage which is applied to the drain electrode in a lateral DMISFET.
SOLUTION: In an open MIS semiconductor device, N+-type source regions 7, whose flat outer forms are octagonal, are selectively formed in a p-type base region 4 so that they are adjacent to the side edges of a P+-type base region 5. The N-type source regions 7 are formed in a forms such that they do not exist on a center line L obtained by connecting the center of an N+-type drain region 6 and the center of the P-type base region 4.
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Inventors:
Yukio Ito
Application Number:
JP35356598A
Publication Date:
November 19, 2001
Filing Date:
December 11, 1998
Export Citation:
Assignee:
NEC
International Classes:
H01L21/336; H01L29/06; H01L29/78; (IPC1-7): H01L29/78
Domestic Patent References:
| JP1140773A | ||||
| JP10233508A | ||||
| JP200031471A | ||||
| JP1174517A | ||||
| JP11330451A | ||||
| JP1174511A | ||||
| JP63289871A | ||||
| JP62189759A | ||||
| JP766392A |
Attorney, Agent or Firm:
Yukio Nishimura