To provide a phase locked loop(PLL) circuit reducing the phase shift of a feedback clock, shortening frequency pulling time and reducing the jitter of a clock to be formed.

In the PLL circuit provided with a 1st phase comparator for comparing the phase of a reference clock with that of a feedback clock, a 2nd phase comparator for comparing the phase of serial data with that of the feedback clock and an oscillator consisting of plural logical gate circuits PGTs and controlled in its oscillating operation in accordance with the phase difference detected by the 1st and 2nd phase comparators and constituted so as to select the 1st phase comparator at first to pull frequency and then the 2nd phase comparator to execute phase matching, the 2nd phase comparator is provided with a delay circuit DLY constituted of logical gate circuits of the same number with that of the oscillator and controlled in its delay time by a common oscillation control signal and a pulse forming circuit (DLT11 to FF22) for generating a signal corresponding to a phase difference between a signal obtained by delaying the serial data by the delay circuit DLY and the feedback clock.