To provide a PLL(phase/locked loop) circuit capable of obtaining a stable loop characteristic regardless of a rate of an input EFM (eight to fourteen modulation) signal and a disk reproducing device using it.
Although the PLL circuit of the disk reproducing device forms a feedback loop consisting of a phase comparator 64, an LPF(low-pass filter) 65, a loop gain amplifier 66 and a VCO(voltage controlled oscillator) 61 by making the EFM signal an input, the feedback loop is composed of LSIs except the LPF requiring flexibility. A part of a resistor in the LPF 65 constituted of the resistor Rb and a capacitor C is incorporated into the output part of the phase comparator 64 in the LSI (semiconductor chip) as the resistor (Ra) 67. An effect due to on-resistance of a transistor is eliminated apparently, and phase comparison information is transmitted correctly to a next stage. Thus, the stable loop characteristic is obtained regardless of the rate of the input EFM signal.
JPS58164008 | DIGITAL SIGNAL MODULATING AND DEMODULATING DEVICE |
JP2002368610 | PLL CIRCUIT |
JP2000163889 | CLOCK REGENERATING DEVICE |
SHIMADA HIROSHI
JPS63279313A | 1988-11-16 |
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