To realize a low jitter operation in a PLL or a DLL circuit by properly detecting the synchronization of two signals, a reference clock signal and a clock signal to be compared therewith, with a phase differential signal being continuously output by a phase comparator which compares the phases of these two signals.

A synchronization determination circuit (15) comprises a phase advancing/phase lagging determination circuit (158) which, by detecting whether the phase of a feedback clock signal (V) is advancing or lagging relative to the phase of a reference clock signal (R), outputs a phase advancing detection signal (DOWN) or a phase lagging detection signal (UP) for a period equal to the difference in phase between the two signals; a phase advancing period counting unit (155) which starts counting from an initial value for a period during which a phase advancing detection signal (DOWN) is output; a phase lagging period counting unit (156) which starts counting from an initial value for a period during which a phase lagging detection signal (UP) is output; and a phase synchronization determination unit (157) which, when a number of times the count value of the phase advancing period counting unit or phase lagging period counting unit did not reach a first specified value exceeds a second specified value, outputs a phase synchronization detection signal (P_DET).