To solve a problem in which malfunction occurs if an input signal DATA has a duty distortion when clock signals ICLK and QCLK are sampled at the leading-edge and trailing-edge change point of an input signal DATA.

A PLL circuit 10 is equipped with a phase detection circuit 11 and a frequency detection circuit 12. The frequency detection circuit 12 is composed of a D-FF 124 which samples a clock signal ICLK at the leading- edge change point (or trailing-edge change point) of an input signal DATA in each cycle synchronizing with the input signal DATA, a D-FF 125 which also samples a clock signal QCLK, and a control logic circuit 126 which performs the logical operations of the signals sampled by the D-FFs 124 and 125 and the signals which are sampled next. An UP pulse signal or a DOWN pulse signal is generated on the basis of the logical operation result of the control logic circuit 126.