Title:
PLL CIRCUIT WITH LOCK MAINTAINING CIRCUIT
Document Type and Number:
Japanese Patent JP2794165
Kind Code:
B2
Abstract:
PURPOSE: To provide a PLL circuit with a lock maintaining circuit which stably maintains the lock state and has a low current consumption.
CONSTITUTION: A device is provided with a reference counter 1 which processes a reference signal Ref, a programmable counter 2 which processes a voltage controlled oscillation signal VCO, a phase detector 3 which detects signals of the reference counter 1 and the programmable counter 2, a lock maintaining circuit 9 which maintains the lock state based on the signal from the phase detector 3, and a refresh clock generator 12 which generates a refresh clock based on the signal of the reference counter 1, and transistors 15 and 17 pass the reference signal Ref and the voltage controlled oscillation signal VCO based on signals of the lock maintaining circuit 9 and the refresh clock generator 12.
Inventors:
HO DAISEI
Application Number:
JP2216095A
Publication Date:
September 03, 1998
Filing Date:
February 10, 1995
Export Citation:
Assignee:
ERU JII SEMIKON CO LTD
International Classes:
H03L7/18; H03L7/00; H03L7/08; H03L7/089; H03L7/095; H03L7/14; H03L7/183; (IPC1-7): H03L7/18
Domestic Patent References:
| JP5308285A | ||||
| JP1206725A |
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)
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