To stabilize the operation of a PLL circuit.

A tuning voltage output step 2 of the PLL circuit is connected to a base of a transistor Q1, and an emitter of the transistor Q1 is connected to a VCO 4. A base/emitter voltage Vbe of the transistor Q1 is added to a tuning voltage VT outputted by the tuning voltage output step 2 and becomes a control voltage TV'=VT+Vbe of the VCO. In the PLL circuit in which the VCO of a type not to be oscillated in the case of VT=0V is mounted, even when the TV is started from 0V at the time of turning on a power source, the VCO is oscillated by VT' so that system operation is not disabled.