Title:
PLL CIRCUIT
Document Type and Number:
Japanese Patent JP3469827
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To secure the phase comparing operation of a PLL circuit.
SOLUTION: When Q terminal outputs of D type flip-flops 101 and 102 vary to high level as a reference frequency signal A and a frequency-division signal rise, an RS type flip-flop outputs a low-level reset signal. As the reset signal is generated, the D type flip-flops 101 and 102 are reset and when the Q terminal outputs both vary to the low level, the RS flip-flop outputs a high-level set signal. As the set signal is generated, the D type flip-flops 101 and 102 are released from being reset. Consequently, a wiring resistance 107 can be ignored and one of a P channel MOSFET 6 and an N channel MOSFET 7 turns on by the phase difference between the reference frequency signal A and frequency division signal to perform charging and discharging operation.
Inventors:
Toshikazu Furukawa
Masaaki Sato
Masaaki Sato
Application Number:
JP22326599A
Publication Date:
November 25, 2003
Filing Date:
August 06, 1999
Export Citation:
Assignee:
Sanyo Electric Co., Ltd.
International Classes:
G06F1/06; H03K5/26; H03L7/089; (IPC1-7): H03L7/089; H03K5/26
Domestic Patent References:
| JP221724A | ||||
| JP63119318A |
Attorney, Agent or Firm:
Masamasa Shibano
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