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Title:
PLL CIRCUIT
Document Type and Number:
Japanese Patent JPH05191275
Kind Code:
A
Abstract:

PURPOSE: To improve the operation stability without increasing the accuracy of a capacitor and a loop gain by providing a capacitor close to a voltage controlled oscillator (VCO), converting the capacitance into an electric signal and applying correction to an input control signal of the VCO with the electric signal.

CONSTITUTION: An external input clock 1 is converted into a pulse width signal by an integration device 9 and a voltage comparator 10, the pulse width signal is smoothed into a DC voltage by a charge pump circuit 11 and a low pass filter 12 and the smoothed signal is converted into a current by a V/I converter 13 and used for a correction value for a control signal inputted to the VCO 1. A voltage outputted from the low pass filter 12 is changed depending on the dispersion in the capacitor of the integration device 9 and the output signal is used for the correction signal to compensate the dispersion in the capacitance of the capacitor in the VCO. Moreover, the output signal of the VCO is in following to the input clock to expand the effective capture range.


Inventors:
DOI KOJI
Application Number:
JP2179092A
Publication Date:
July 30, 1993
Filing Date:
January 10, 1992
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03L7/08; H03L7/10; (IPC1-7): H03L7/08; H03L7/10
Attorney, Agent or Firm:
Yusuke Omi



 
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