PURPOSE: To surely synchronize a synchronizing signal generated synchronously with clock signals A, B with a control signal by controlling a frequency of the clock signal B so that the phase of the clock signals A, B is locked with each other based on a phase error resulting from comparison of the phases of the clock signals A, B.

CONSTITUTION: An AND circuit 40 ANDs horizontal synchronizing signals HD delayed by one clock period at FFs 39, 41 based on a clock signal (Ck) A whose frequency is 32.4MHz and outputs a signal by two periods of the Ck A. A frequency division counter 31 receiving 11 periods of a clock signal Ck B whose frequency is 44.55MHz outputted from a VCO 26 is cleared by a NAND circuit 32, and an OR circuit 42 ORs outputs of the circuits 40, 32. As a result, an output of the OR circuit 42 goes to an L level by one period of the clock signal Ck B synchronously with the horizontal synchronizing signal HD to surely reset a frequency division counter 36 of the 44.55MHz group. Thus, a read control signal of the 44.55MHz group given to a time base expansion line memory is surely synchronized with the horizontal synchronizing signal whose frequency is 32.4MHz. Thus, the excellent PLL circuit is configured.